1. Field of the Invention
The present invention relates to a structure of a thin film transistor (TFT) and to a process for fabricating the same. The present invention also relates to a process for fabricating an insulated gate semiconductor device on an insulator substrate and to a process for fabricating an integrated circuit (IC) obtained by assembling a plurality of said insulated gate semiconductor devices on an insulator substrate. The term “insulator substrate” as referred herein means any article having an insulating surface, and, if not particularly stated, it encompasses not only those made of insulating materials such as glass, but also articles having thereon an insulator layer and made of a material such as a semiconductor and a metal. The semiconductor device according to the present invention is useful as TFTs of active matrices of liquid crystal displays, driver circuits of image sensors, or SOI (silicon on insulator) integrated circuits and conventional semiconductor integrated circuits (e.g., microprocessors and micro controllers, micro computers, and semiconductor memories).
2. Prior Art
Recently, intensive study is performed on the process for fabricating an insulated gate semiconductor device (MOSFET) on an insulator substrate. The integrated circuits (ICs) of this type being established on an insulator substrate are advantageous considering their suitability to high speed drive, because such ICs on an insulator need not suffer stray capacitance. In contrast to these ICs, the operation speed of a conventional IC is limited by a stray capacitance, i.e., a capacitance between the connection and the substrate. The MOSFETs having formed on an insulator substrate and comprising a thin film active layer is called a thin film transistor (TFT). Those TFTs are indispensable in forming multilayered integrated circuits. At present, a TFT can be found in a conventional semiconductor IC, for example, as a load transistor of an SRAM.
Some of the recent products, for example, driver circuits for optical devices such as liquid crystal displays and image sensors, require a semiconductor IC to be formed on a transparent substrate. TFTs can be found assembled therein, however, the ICs must be formed over a wide area, and a low temperature process for fabricating TFTs is thereby required. Furthermore, in devices having a plurality of terminals each connected with semiconductor ICs on an insulator substrate, for instance, it is proposed to reduce the mounting density by forming the lower layers of the semiconductor IC or the entire semiconductor IC itself monolithically on the same insulator substrate.
Conventionally, TFTs of high quality have been obtained by thermally annealing an amorphous or semi-amorphous film, or a microcrystalline film at a temperature in the range of from 450 to 1,200° C. to produce a high performance semiconductor film (i.e., a semiconductor film having sufficiently high mobility). An amorphous TFT using an amorphous material for the semiconductor film can also be fabricated; however, its application field is greatly limited because of its inferior operation speed ascribed to an extremely low mobility of 5 cm2/Vs or even lower, about 1 cm2/Vs in general, or because of its inability of providing a P-channel TFT (PTFT). A TFT having a mobility of 5 cm2/Vs or higher is available only after annealing the semiconductor film at a temperature in the range of from 450 to 1,200° C. A PTFT can be fabricated only after subjecting the film to such annealing treatments.
However, in a thermal process involving heating at a high temperature, in particular, only strictly selected substrate material can be used. More specifically, a so-called high temperature process which involves high temperature heating in the range of from 900 to 1,200° C. is advantageous, because it allows the use of a high quality film obtainable by thermal oxidation as a gate dielectric, but substrates applicable to the high temperature process are confined to those made from expensive materials such as quartz, sapphire, and spinel, which are not suited for substrates to use in large area applications.
In contrast to the high temperature process above, a low temperature process, in which maximum temperature is in the range of from 450 to 750° C., allows the use of substrate materials selected from a wider variety. However, such a process requires long annealing, and moreover, the sheet resistance of the source/drain remains high due to insufficient activation of the impurities. There is also an attempt of crystallizing the active layer and of activating source/drain by irradiating a laser beam and the like (this process is denoted as “laser process”, hereinafter), however, it has been found also difficult to lower the sheet resistance. In fabricating a TFT having a field mobility higher than 150 cm2/Vs, in particular, it is essential to achieve a sheet resistance of not higher than 200 Ω/cm2.
It is also well known to use TFTs in devices such as active matrix-driven liquid crystal display devices and image sensors comprising glass substrates having integrated elements thereon. FIG. 9 schematically shows a cross sectional view of a conventional TFT. FIG. 12 shows schematically a cross sectional view of another conventional TFT and an example of the step sequential process for fabricating the same. FIG. 9(A) shows an insulated gate field effect transistor (referred to simply hereinafter as a “TFT”) using a thin film silicon semiconductor provided on a glass substrate. Referring to FIG. 9(A), a silicon oxide film 62 about 2,000 Å in thickness as a base is formed on a glass substrate 61, and an active layer comprising a silicon semiconductor film having source/drain regions 63 and 65 together with a channel forming region 64 is formed on the silicon oxide film 62. An amorphous or crystalline (polycrystalline or microcrystalline) silicon semiconductor layer is provided at a thickness of about 1,000 Å.
A silicon oxide film 66 about 1,000 Å in thickness as a gate insulator film is formed on the active layer. An aluminum gate contact 67 is established thereon, and it is surrounded by an oxide layer 68 about 2,000 Å in thickness formed by anodic oxidation. An interlayer insulator 69 is formed using silicon oxide, etc., and source/drain contacts 70 and 71, as well as a contact hole 72 to the gate contact 67 are established therein. In FIG. 9(A), the contact hole 72 connected to the gate contact 67 is not in the same plane as that on which the source/drain contacts 70 and 71 are located, but is provided either beyond or at the front of the plane.
The structure shown in FIG. 9(A) is characterized in that an offset gate region can be formed in a self aligned manner by controlling the anodic oxidation of the aluminum gate contact 67. The thickness 73 of the oxide layer 68 around the gate contact 67 depends on this controlled thickness which results from anodic oxidation. More specifically, an offset region corresponding to the thickness of the oxide layer 68 can be established by implanting impurity ions for forming source/drain regions after forming the oxide layer 68.
However, because of the diffusion of the impurities, the boundary between the channel forming region 64 and the source/drain regions 63 and 65 in practice is located at a portion nearer to the channel forming portion than the portion corresponding to the edge of the oxide layer 68. Thus, the thickness of the oxide layer 68 must be determined taking the influence of diffusion into consideration. In general, the oxide layer 68 must be formed thicker than the length of the desired offset gate.
The contact holes connected to the source/drain regions 63 and 65 must be perforated with care not to be overetched. An excessive etching beyond the boundary between the silicon oxide film 66 and into the peripheral portion of the contact hole allows aluminum to diffuse into the etched peripheral portion upon forming the aluminum contacts 70 and 71, and in extreme cases, the diffusion of aluminum inside the vicinity of the channel forming region 64 impairs the characteristics and the reliability of the TFT.
On the other hand, the sheet resistance between the channel forming region 64 and the contact portions of the source/drain regions becomes a problem with increasing distance 74 therebetween. This problem may be solved by shortening the distance 74, however, this countermeasure is limited to a certain extent because too short a distance reversely impairs the precision upon matching the mask. This is a serious problem particularly when a glass substrate is used, because shrinking of the glass substrate occurs during the heating steps (various types of annealing steps are indispensable) to give unfavorable results upon matching the mask. For instance, a 10-cm square or a larger glass substrate readily shrinks for about several micrometers upon heat treatment at about 600° C. Accordingly, in a present-day process, a margin of about 20 μm is always included in the distance 74.
Considering the problem of overetching upon forming contact holes connected to the source/drain regions, on the other hand, it is not possible to excessively shorten the distance 74. As described in the foregoing, the conventional TFTs suffer the following disadvantages:
(1) Problems are associated with the formation of contact holes connected to the source/drain regions; and
(2) In view of the above problem (1), sheet resistance of the source/drain regions is also a problem because the contact hole cannot be located in the vicinity of the channel forming region.
As a means of overcoming the shortcomings (1) and (2) of the conventional TFTs as mentioned hereinbefore, a TFT of a structure shown in FIG. 9(B) is proposed. This TFT comprises a gate contact 67 comprising aluminum as the principal component and is surrounded by an oxide layer 68 formed by anodic oxidation in the similar manner as in the TFT shown in FIG. 9(A). Accordingly, source/drain contacts 70 and 71 are provided in tight contact with the oxide layer 68. In this structure, however, the gate contact is located next to source/drain contacts 70 and 71 with only the oxide layer 68 incorporated therebetween. Accordingly, a parasitic capacity which forms by the incorporation of the oxide layer 68 makes the operation unstable and lowers the reliability of the TFT. This problem can be overcome by increasing the thickness of the oxide layer 68. However, since the thickness of the oxide layer 68 corresponds to the length of the offset gate, the thickness thereof can not be simply increased as desired. In addition, pinholes in the oxide layer 68 give occasion to leakage between the gate contact and the source/drain contacts. At any rate, this type of TFT is not practically feasible.
FIG. 12 shows another insulated gate field effect transistor (referred to simply hereinafter as “TFT”) comprising a thin film silicon semiconductor on a glass substrate. The process for fabricating the structure is described below. Referring to FIG. 12(A), a silicon oxide film 1302 about 2,000 Å in thickness is formed on a glass substrate 1301, and further, an island-like active layer 1303 made of a silicon semiconductor film is formed to a thickness of about 500 to 2,000 Å on the silicon oxide film 1302. The silicon semiconductor film is either amorphous or crystalline (e.g., polycrystalline and microcrystalline). A silicon oxide film 1304 about 1,000 to 1,500 Å in thickness is formed further on the active layer to give a gate insulator film.
Then, a gate contact 1305 is formed from an impurity-doped polycrystalline silicon (polysilicon), tantalum, titanium, aluminum, etc. (see FIG. 12(B)).
Source/drain regions (impurity regions) 1306 are formed in the active layer 1303 in a self aligned manner by introducing impurities such as phosphorus and boron. This is performed using processes such as ion doping, employing the gate contact as the mask. The active region under the gate contact and which remains undoped provides a channel forming region 1307 (see FIG. 12(C)).
The doped impurities are then activated by irradiating a laser beam or by using heat sources such as flash lamps (see FIG. 12(D)).
Then, a silicon oxide film is formed by a process such as plasma CVD and APCVD to give the interlayer insulator 1307. Furthermore, contact holes are perforated in the source/drain regions through the interlayer insulator to provide connection and contacts 1308 connected to the source/drain using a metallic material such as aluminum (see FIG. 12(E)).
In a conventional TFT as described in the foregoing, it is essential to lower the sheet resistance of the source/drain regions to improve the TFT properties, particularly, the field mobility and the sub-threshold characteristics (S value). The following measures were proposed to achieve the requirement:
(1) Increasing the concentration of the doped impurities;
(2) Increasing the activation energy (the intensity of a laser beam or a flash lamp) to a sufficiently high value; and
(3) Decreasing the distance (indicated with “z” in FIG. 12(E)) between the channel forming region 1307 and the metal contact 1308.
With respect to the measure (1) above, an increase in the doped impurity concentration signifies an increase in the treatment duration and hence, a decrease in throughput. Moreover, the damage of the active layer and the gate insulator film 1304 increases with increasing concentration of the doped impurities. A process such as ion doping and plasma doping, which comprises producing a plasma of the impurities and accelerating it for impurity implantation, is a superior method of mass production. However, the accelerated ions contain a plurality atoms such as of hydrogen to result in a heat up of the substrate. This problem becomes particularly distinct with increasing density of the plasma. Accordingly, problems occur upon doping, including heating up of the device and thereby damaging it, and, in case a photoresist is used, carbonizing it and thereby making its removal difficult.
Concerning the measure (2) above, too intense an energy not only causes peeling off of the active layer or the gate contact and thereby lowering the yield of the TFT, but also impairs the throughput. In using a laser, for instance, it is necessary to intensely converge the beam to increase the energy density, because the energy itself cannot be greatly intensified. This inevitably decreases the beam area, and the treatment hence requires a longer duration of irradiation to cover an area of the same size.
The measure (3) depends on the precision of matching the mask, and no considerable improvement can be expected. This is a serious problem particularly when a glass substrate is used, because shrinking of the glass substrate occurs during the heating steps (various types of annealing steps are indispensable in the process) to give unfavorable results upon matching the mask. For instance, a 10 cm square or larger glass substrate readily shrinks for about several micrometers upon heat treatment at about 600° C. Accordingly, in a present-day process, a margin of about 20 μm is always included in the distance z. When z is small, moreover, a large parasitic capacity generates between the gate contact 1305 and the source/drain contacts 1308 to unfavorably affect the properties of the TFT.
On forming contact holes in the source/drain regions 1306, it is required that the etching is conducted slightly in excess to assure the formation of the contact holes. Accordingly, the distance z cannot be shortened to a large extent. As described in the foregoing, it is next to impossible to further lower the parasitic resistance of the source/drain regions so long a prior art process is employed.